1. Field of the Invention
This invention relates to memory cells and methods for manufacture thereof. Specifically, the invention relates to a method for manufacturing memory cells free of ONO fence material.
2. Discussion of Related Art
FIG. 1 shows a cross-sectional view of a portion of a core cell in a NAND-type flash memory device. Fabrication of a NAND-type flash memory device involves depositing a lower polysilicon ("poly I") layer 2 over tunnel oxide layer 8 and etching it so as to provide the structure shown over active region 10 of FIG. 2.
The exact profile of the etched structure of poly I layer 2 is hard to control. The profile depends on the photoresist profile and the etch process. Consequently, the overlap between the structure of poly I layer 2 and the underlying core field oxide regions 12 vary. FIG. 2 depicts, for example, an edge of the structure of poly I layer 2 not overlapping a flat region of a core field oxide region 12. Consequently, a recess 14 forms in poly I layer 2 over a sloping portion of core field oxide region 12 that may appear along the entire edge of poly I layer 2. For example, recess 14 can be caused by a horizontal etching of poly I layer 2. Recess 14 harbors ONO 4 and poly II layer 6 materials from subsequent ONO 4 and poly II layer 6 depositions.
After depositing and etching poly I layer 2; as shown in FIG. 1, a triple layer consisting of an oxide-nitride-oxide ("ONO") stack, shown as ONO 4, and polysilicon ("poly II") layer 6 are provided above the poly I layer 2 structure. A tungsten silicide layer 93 and a silicon oxy-nitride (SiON) layer 94 are formed next.
FIG. 3 corresponds to a top view of the structure of FIG. 1. In FIG. 3, core field oxide regions 40a and 40b correspond to portions of core field oxide regions 12 of FIG. 1; active region 42 corresponds to a portion of active region 10 of FIG. 1; and poly I layer 66 corresponds to a portion of poly I layer 2 of FIG. 1.
Next, successive layers of material are removed from shaded region 100 of the structure 58 of FIG. 3 ("removal steps"): SiON layer 94, tungsten silicide layer 93, poly II layer 6, ONO 4, and poly I layer 2. The ONO 4 layer and poly I layer 2 may be removed by "anisotropic" etching techniques.
However, if the poly II layer 6 forms in the recess 14, it may not be removed from the recess 14 in shaded region 100 of FIG. 3. The poly II layer 6 in the recess 14 also may shield ONO 4 from removal from the recess 14 present in shaded region 100 of FIG. 3. Remaining ONO 4 ("ONO fence" 16) further shields poly I layer 2 from removal from the shaded region 100 of FIG. 3.
Alternatively, edges of the etched poly I layer 2 may overlap with top, flat portions of core field oxide regions 12 and consequently recesses 14 may be absent from the poly I layer 2 as shown in FIG. 4. However, because of anisotropic etching of ONO 4 layer, following removal of the ONO 4 from shaded region 100 of the structure 58 of FIG. 3, ONO fences 16 may remain.
FIG. 5A shows a top view of the structure 60 of FIG. 4 after the removal steps described earlier. ONO fences 16 appear, for example, at positions 48a, 48b, 48c, and 48d of FIG. 5A. ONO fences 16 shield some poly I layer 2 material from removal during the removal steps. Remaining poly I materials present, for example, at positions 48a, 48b, 48c, and 48d of FIG. 5A ("polystringers" 18) electrically short NAND-type memory cells.
FIG. 5B depicts a cross section of the structure 62 of FIG. 5A showing ONO fence 16 and polystringers 18. Structure 70 of FIG. 5B corresponds, for example, to a cross section along line X2--X2 of structure 62 of FIG. 5A. In that cross section, core field oxide regions 12 correspond to portions of core field oxide regions 40a and 40b of FIG. 5A, and active region 10 corresponds to a portion of active region 42 of FIG. 5A. Poly I layer 46 of FIG. 5A corresponds to a portion of poly I layer 2 of FIG. 4.
FIG. 6A depicts a matrix of NAND-type flash memory core cells 22 with polystringers occurring, for example, at positions 20. Consequently, as shown in FIGS. 6A and 6B, following etching, an "ONO fence" 16, portions of poly II layer 6, and portions of poly I layer 2 may remain at positions 20.
FIG. 6B corresponds, for example, to a cross section along line X--X of the structure of FIG. 6A. FIG. 6B depicts a position 20 that may include portions of poly II layer 6 and portions of poly I layer 2 that constitute polystringers 18 that. electrically short NAND-type flash memory core cells 22, thereby rendering the flash memory core cells inoperable.